9–48
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–14. FPP Timing Parameters for Cyclone III Device Family
Symbol
t
CD2CU
t
CD2UMC
Parameter
CONF_DONE
high to
CLKUSR
enabled
CONF_DONE
high to user mode with
CLKUSR
option on
(Part 2 of 2)
Minimum
4 × maximum
DCLK
period
t
CD2CU
+ (initialization clock
cycles ×
CLKUSR
period)
Maximum
—
—
Unit
—
—
Notes to
(1) This value is applicable if users do not delay configuration by extending the
nCONFIG
or
nSTATUS
low pulse width.
(2) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting up the device.
(3) Cyclone III EP3C5, EP3C10, EP3C16, EP3C25, and EP3C40 devices support a
DCLK
f
MAX
of 133 MHz. Cyclone III EP3C55, EP3C80, EP3C120 and
all the Cyclone III LS devices support a
DCLK
f
MAX
of 100 MHz.
(4) For more information about the initialization clock cycles required in Cyclone III device family, refer to
JTAG Configuration
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use the JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates
.sofs
that are used for JTAG
configuration with a download cable in the Quartus II software programmer.
f
For more information about JTAG boundary-scan testing, refer to the
chapter.
For the Cyclone III device, JTAG instructions have precedence over any other device
configuration modes. Therefore, JTAG configuration can take place without waiting
for other configuration modes to complete. For example, if you attempt JTAG
configuration of a Cyclone III device during PS configuration, PS configuration
terminates and JTAG configuration begins. If the Cyclone III device MSEL pins are set
to AS mode, the Cyclone III device does not output a
DCLK
signal when JTAG
configuration takes place.
1
For the Cyclone III LS device, JTAG programming is disabled if the device was
already configured using the PS or AS mode. After POR, the Cyclone III LS device
allows only mandatory JTAG 1149.1 instructions (BYPASS,
SAMPLE/RELOAD, EXTEST,
and
FACTORY).
For more information, refer to
The four required pins for a device operating in JTAG mode are
TDI, TDO, TMS,
and
TCK.
The
TCK
pin has an internal weak pull-down resistor while the
TDI
and
TMS
pins have
weak internal pull-up resistors (typically 25 k). The
TDO
output pin is powered by
V
CCIO
in I/O bank 1. All the JTAG input pins are powered by the V
CCIO
pin. All the
JTAG pins support only LVTTL I/O standard. All user I/O pins are tri-stated during
JTAG configuration.
lists the function of each JTAG pin.
1
The
TDO
output is powered by the V
CCIO
power supply of I/O bank 1.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
