欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP3C16Q144C6ES 参数 Datasheet PDF下载

EP3C16Q144C6ES图片预览
型号: EP3C16Q144C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP3C16Q144C6ES的Datasheet PDF文件第201页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第202页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第203页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第204页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第206页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第207页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第208页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第209页  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–47
FPP Configuration Timing
shows the timing waveform for FPP configuration when using an
external host.
Figure 9–23. FPP Configuration Timing Waveform
t
CF2ST1
t
CFG
nCONFIG
nSTATUS
(2)
CONF_DONE
(3)
t
CF2CD
t
CF2CK
t
STATUS
t
CF2ST0
t
t
ST2CK
CLK
t
CH
t
CL
DCLK
t
DH
(4)
Byte 2
Byte 3
Byte
n-1
DATA[7..0]
Byte 0
Byte 1
Byte
n
(5)
User Mode
User Mode
t
DSU
User I/O Tri-stated
with
internal pull-up resistor
INIT_DONE
t
CD2UM
Notes to
(1) The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG, nSTATUS,
and
CONF_DONE
are at logic-high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds
nSTATUS
low during POR delay.
(3) After power-up, before and during configuration,
CONF_DONE
is low.
(4) Do not leave
DCLK
floating after configuration. It must be driven high or low, whichever is more convenient.
(5)
DATA[7..0]
is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
settings.
lists the FPP configuration timing parameters for Cyclone III device family.
Table 9–14. FPP Timing Parameters for Cyclone III Device Family
Symbol
t
CF2CD
t
CF2ST0
t
CFG
t
STATUS
t
CF2ST1
t
CF2CK
t
ST2CK
t
DSU
t
DH
t
CH
t
CL
t
CLK
f
MAX
t
CD2UM
Parameter
nCONFIG
low to
CONF_DONE
low
nCONFIG
low to
nSTATUS
low
nCONFIG
low pulse width
nSTATUS
low pulse width
nCONFIG
high to
nSTATUS
high
nCONFIG
high to first rising edge on
DCLK
nSTATUS
high to first rising edge of
DCLK
DATA
setup time before rising edge on
DCLK
DATA
hold time after rising edge on
DCLK
DCLK
high time
DCLK
low time
DCLK
period
DCLK
frequency
CONF_DONE
high to user mode
(Part 1 of 2)
Minimum
500
45
230
2
5
0
3.2
3.2
7.5
300
Maximum
500
500
230
230
100
Unit
ns
ns
ns
s
s
s
s
ns
ns
ns
ns
ns
MHz
s
650
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1