Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
8–3
1
Cyclone III device family does not support differential strobe pins, which is an
optional feature in the DDR2 SDRAM device.
f
When you use the Altera Memory Controller MegaCore
®
, the PHY is instantiated for
you. For more information about the memory interface data path, refer to the
page.
1
ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone III device family through the
ALTMEMPHY megafunction because you are not required to route the
DQS
signals on
the global clock buses (because
DQS
is ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data
DQ.
All I/O banks in Cyclone III device family can support
DQ
and
DQS
signals with
DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36. DDR2 and DDR SDRAM interfaces use ×8
mode
DQS
group regardless of the interface width. For wider interface, you can use
multiple ×8
DQ
groups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36
DQ
pins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal which is connected to
the complementary data strobe (DQS or CQ#) pin. You can use any unused
DQ
pins as
regular user I/O pins if they are not used as memory interface signals.
lists the number of
DQS
or
DQ
groups supported on each side of the
Cyclone III device only.
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
Device
Package
Left
144-pin EQFP
Right
Top
Left
EP3C5
164-pin MBGA
Side
Number
×8
Groups
0
0
1
1
0
0
1
Number
×9
Groups
0
0
0
0
0
0
0
0
1
1
2
2
Number
×16
Groups
0
0
0
0
0
0
0
0
0
0
1
1
Number
×18
Groups
0
0
0
0
0
0
0
0
0
0
1
1
Number
×32
Groups
—
—
—
—
—
—
—
—
—
—
—
—
Number
×36
Groups
—
—
—
—
—
—
—
—
—
—
—
—
Bottom
Right
Top
Left
Top
Bottom
Bottom
1
1
1
2
2
256-pin FineLine
BGA/256-pin
Ultra FineLine
BGA
Right
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
