7–20
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Document Revision History
Table 7–6. Document Revision History (Part 2 of 2)
Date
Version
Changes
Changes include addition of BLVD information
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Updated “Introduction” section with BLVDS information.
Updated Figure 7–1 with BLVDS information and added Note 5.
Updated Table 7–1 and added BLVDS information.
Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
Updated Table 7–2 and 7–6.
Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated Note 4 to Figure 7–4.
Updated Note 1 to Figure 7–10.
Updated Note 1 to Figure 7–11.
Updated Note 1 to Figure 7–14.
Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
Updated Note 1 to Figure 7–17.
Updated “LVPECL I/O Support in Cyclone III Devices” section.
Added new Figure 7–18.
Added note that PLL output clock pins do not support Class II type of selected differential
I/O standards.
Added Table 8–3 that lists the number of differential channels which are migratable
across densities and packages.
Updated
(Note 4)
to Figure 7–1.
Updated
(Note 3)
to Table 7–1.
Added new Table 7–3.
Added
(Note 1)
to Figure 7–21.
Added
(Note 1)
to Figure 7–23.
Added chapter TOC and “Referenced Documents” section.
May 2008
1.2
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July 2007
1.1
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March 2007
1.0
Initial release.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
