I/O Structure
Table 2–14. DQS & DQ Bus Mode Support (Part 2 of 2)
Note (1)
Number of
×4 Groups
Number of
Number of
Number of
Device
Package
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
EP2S90 484-pin Hybrid FineLine BGA
780-pin FineLine BGA
8
4
0
4
8
8
4
8
8
8
8
0
0
4
4
0
4
4
4
4
18
36
36
18
36
36
36
36
8
1,020-pin FineLine BGA
18
18
8
1,508-pin FineLine BGA
EP2S130 780-pin FineLine BGA
1,020-pin FineLine BGA
18
18
18
18
1,508-pin FineLine BGA
EP2S180 1,020-pin FineLine BGA
1,508-pin FineLine BGA
Notes to Table 2–14:
(1) Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]pfeed the phase circuitry on the top of the device and
clock pins CLK[7..4]pfeed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
Figure 2–56 illustrates the phase-shift reference circuit control of each
DQS delay shift on the top of the device. This same circuit is duplicated
on the bottom of the device.
2–82
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
