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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
Figure 2–53. Input Timing Diagram in DDR Mode  
Data at  
input pin  
B0  
A0 B1 A1 B2 A2 B3 A3 B4  
CLK  
A0  
B0  
A1  
B1  
A2  
B2  
A3  
B3  
Input To  
Logic Array  
When using the IOE for DDR outputs, the two output registers are  
configured to clock two data paths from ALMs on rising clock edges.  
These output registers are multiplexed by the clock to drive the output  
pin at a ×2 rate. One output register clocks the first bit out on the clock  
high time, while the other output register clocks the second bit out on the  
clock low time. Figure 2–54 shows the IOE configured for DDR output.  
Figure 2–55 shows the DDR output timing diagram.  
Altera Corporation  
May 2007  
2–79  
Stratix II Device Handbook, Volume 1  
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