Stratix II Architecture
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–31 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 2–31. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
CLK[11..8]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks RCLK[7..0]in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0]input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLKclock pins symmetrically drive the RCLKnetworks in
a particular quadrant, as shown in Figure 2–32.
Altera Corporation
May 2007
2–49
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
