Stratix II Architecture
The LAB row source for control signals, data inputs, and outputs is
shown in Table 2–7.
Table 2–7. DSP Block Signal Sources & Destinations
LAB Row at
Interface
Control Signals Generated
Data Inputs Data Outputs
0
clock0
aclr0
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
ena0
mult01_saturate
addnsub1_round/ accum_round
addnsub1
signa
sourcea
sourceb
1
2
3
clock1
aclr1
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
A2[17..0]
B2[17..0]
OC[17..0]
OD[17..0]
clock2
aclr2
ena2
mult23_saturate
addnsub3_round/ accum_round
addnsub3
sign_b
sourcea
sourceb
A3[17..0]
B3[17..0]
OE[17..0]
OF[17..0]
clock3
aclr3
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
f
See the DSP Blocks in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook, for more information on DSP blocks.
Altera Corporation
May 2007
2–47
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
