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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 5–4. Stratix II Device DC Operating Conditions (Part 2 of 2)  
Note (1)  
Symbol  
Parameter  
Conditions  
Minimum Typical Maximum Unit  
ICCI00  
VCCIO supply current  
(standby)  
VI = ground, no  
load, no toggling  
inputs  
EP2S15  
EP2S30  
EP2S60  
EP2S90  
EP2S130  
EP2S180  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
25  
35  
50  
75  
90  
1
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
50  
mA  
mA  
mA  
mA  
mA  
mA  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
TJ = 25° C  
RCONF (4) Value of I/O pin pull-up  
resistor before and  
Vi = 0; VCCIO = 3.3 V  
Vi = 0; VCCIO = 2.5 V  
Vi = 0; VCCIO = 1.8 V  
Vi = 0; VCCIO = 1.5 V  
Vi = 0; VCCIO = 1.2 V  
10  
15  
30  
40  
50  
70  
during configuration  
100  
150  
170  
2
Recommended value of  
I/O pin external  
pull-downresistorbefore  
and during configuration  
Notes to Table 5–4:  
(1) Typical values are for TA = 25°C, VCCINT = 1.2 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.  
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all  
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).  
(3) Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power  
Estimator (available at www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum  
values. See the section “Power Consumption” on page 5–20 for more information.  
(4) Pin pull-up resistance values are lower if an external source drives the pin higher than VCCIO  
.
I/O Standard Specifications  
Tables 5–5 through 5–32 show the Stratix II device family I/O standard  
specifications.  
Table 5–5. LVTTL Specifications (Part 1 of 2)  
Symbol  
VCCIO (1)  
VIH  
Parameter  
Output supply voltage  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Conditions  
Minimum  
3.135  
1.7  
Maximum  
3.465  
4.0  
Unit  
V
V
VIL  
–0.3  
0.8  
V
VOH  
IOH = –4 mA (2)  
2.4  
V
5–4  
Altera Corporation  
May 2007  
Stratix II Device Handbook, Volume 1  
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