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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
The number of M512 RAM, M4K RAM, and DSP blocks varies by device  
along with row and column numbers and M-RAM blocks. Table 2–1 lists  
the resources available in Stratix II devices.  
Table 2–1. Stratix II Device Resources  
M512 RAM  
Columns/Blocks Columns/Blocks  
M4K RAM  
M-RAM  
Blocks  
DSP Block  
Columns/Blocks Columns  
LAB  
Device  
LAB Rows  
EP2S15  
EP2S30  
EP2S60  
EP2S90  
EP2S130  
EP2S180  
4 / 104  
6 / 202  
7 / 329  
8 / 488  
9 / 699  
11 / 930  
3 / 78  
4 / 144  
5 / 255  
6 / 408  
7 / 609  
8 / 768  
0
1
2
4
6
9
2 / 12  
2 / 16  
3 / 36  
3 / 48  
3 / 63  
4 / 96  
30  
49  
26  
36  
51  
68  
87  
96  
62  
71  
81  
100  
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,  
LAB control signals, local interconnect, and register chain connection  
lines. The local interconnect transfers signals between ALMs in the same  
LAB. Register chain connections transfer the output of an ALM register to  
the adjacent ALM register in an LAB. The Quartus® II Compiler places  
associated logic in an LAB or adjacent LABs, allowing the use of local,  
shared arithmetic chain, and register chain connections for performance  
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.  
Logic Array  
Blocks  
Altera Corporation  
May 2007  
2–3  
Stratix II Device Handbook, Volume 1