Functional Description
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
TM
transfer at up to 1 Gbps using LVDS or HyperTransport technology I/O
standards.
Figure 2–1 shows an overview of the Stratix II device.
Figure 2–1. Stratix II Block Diagram
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded LVDS, HyperTransport & other
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
Memory Functions
I/O Standards
IOEs
LABs
IOEs
LABs
IOEs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
M-RAM Block
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
DSP
Block
2–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
