DC Characteristics and Timing Specifications
Table 5–45. Maximum Output Clock Toggle Rate on Cyclone II Devices (Part 4 of 4)
Maximum Output Clock Toggle Rate on Cyclone II Devices (MHz)
Dedicated Clock
Column I/O Pins (1)
Row I/O Pins (1)
Drive
Outputs
I/O Standard
Strength
–6
–7
–8
–6
–7
–8
–6
–7
–8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
1.5V_
DIFFERENTIAL_HSTL
_CLASS_I
8 mA
210
220
230
210
170
180
190
170
140
150
160
140
210
—
170
—
140
—
210
—
170
—
140
—
10 mA
12 mA
16 mA
—
—
—
—
—
—
1.5V_
—
—
—
—
—
—
DIFFERENTIAL_HSTL
_CLASS_II
LVDS
—
—
—
—
—
—
400
400
400
380
80
340
340
340
320
80
280
280
280
260
80
400
400
400
380
—
340
340
340
320
—
280
280
280
260
—
400
400
400
380
—
340
340
340
320
—
280
280
280
260
—
RSDS
MINI_LVDS
SIMPLE_RSDS
1.2V_HSTL
1.2V_
80
80
80
—
—
—
—
—
—
DIFFERENTIAL_HSTL
PCI
—
—
—
—
—
—
—
—
350
350
360
315
315
300
280
280
250
350
350
360
315
315
300
280
280
250
PCI-X
LVTTL
OCT_25_
OHMS
360
300
250
LVCMOS
OCT_25_
OHMS
360
240
290
240
290
300
200
240
200
240
250
160
200
160
200
360
240
290
240
290
300
200
240
200
240
250
160
200
160
200
360
240
290
—
300
200
240
—
250
160
200
—
2.5V
OCT_50_
OHMS
1.8V
OCT_50_
OHMS
SSTL_2_CLASS_I
SSTL_18_CLASS_I
OCT_50_
OHMS
OCT_50_
OHMS
—
—
—
Note to Table 5–45:
(1) This is based on single data rate I/Os.
Altera Corporation
February 2008
5–51
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
