Timing Specifications
Table 5–44. Maximum Input Clock Toggle Rate on Cyclone II Devices (Part 2 of 2)
Maximum Input Clock Toggle Rate on Cyclone II Devices (MHz)
Dedicated Clock
Inputs
Column I/O Pins
–6 –7 –8
Row I/O Pins
–7
I/O Standard
–6
–8
–6
–7
–8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
DIFFERENTIAL_SSTL_18_
CLASS_I
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
DIFFERENTIAL_SSTL_18_
CLASS_II
1.8V_DIFFERENTIAL_HSTL_
CLASS_I
1.8V_DIFFERENTIAL_HSTL_
CLASS_II
1.5V_DIFFERENTIAL_HSTL_
CLASS_I
1.5V_DIFFERENTIAL_HSTL_
CLASS_II
LVPECL
—
—
402
90
—
402
80
—
402
—
—
402
—
—
402
—
402
402
110
110
402
402
90
402
402
80
LVDS
402
110
110
1.2V_HSTL
1.2V_DIFFERENTIAL_HSTL
90
80
—
—
—
90
80
Table 5–45. Maximum Output Clock Toggle Rate on Cyclone II Devices (Part 1 of 4)
Maximum Output Clock Toggle Rate on Cyclone II Devices (MHz)
Dedicated Clock
Column I/O Pins (1)
Row I/O Pins (1)
Drive
Outputs
I/O Standard
Strength
–6
–7
–8
–6
–7
–8
–6
–7
–8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
LVTTL
4 mA
120
200
280
290
330
360
100
170
230
240
280
300
80
120
200
280
290
330
360
100
170
230
240
280
300
80
120
200
280
290
330
360
100
170
230
240
280
300
80
8 mA
140
190
200
230
250
140
190
200
230
250
140
190
200
230
250
12 mA
16 mA
20 mA
24 mA
5–48
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
