DC Characteristics and Timing Specifications
Table 5–46. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 4)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Dedicated Clock
Column I/O Pins
Row I/O Pins
Drive
Outputs
I/O Standard
Strength
–6 –7 –8
–6
–7
–8
–6
–7
–8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
SSTL_2_CLASS_I
SSTL_18_CLASS_I
OCT_50
_OHMS
67
69
70
25
42
60
25
42
60
OCT_50
_OHMS
30
33
36
47
49
51
47
49
51
High Speed I/O Timing Specifications
The timing analysis for LVDS, mini-LVDS, and RSDS is different
compared to other I/O standards because the data communication is
source-synchronous.
You should also consider board skew, cable skew, and clock jitter in your
calculation. This section provides details on the timing parameters for
high-speed I/O standards in Cyclone II devices.
Table 5–47 defines the parameters of the timing diagram shown in
Figure 5–3.
Table 5–47. High-Speed I/O Timing Definitions (Part 1 of 2)
Parameter
Symbol
Description
High-speed clock
Duty cycle
fHSCKLK High-speed receiver and transmitter input and output clock frequency.
tDUTY Duty cycle on high-speed transmitter output clock.
HSIODR High-speed receiver and transmitter input and output data rate.
High-speed I/O data rate
Time unit interval
TUI
TUI = 1/HSIODR.
Channel-to-channel skew TCCS
The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the
TCCS measurement.
TCCS = TUI – SW – (2 × RSKM)
Altera Corporation
February 2008
5–55
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
