Cyclone II Architecture
Each global clock network has a clock control block to select from a
number of input clock sources (PLL clock outputs, CLK[] pins, DPCLK[]
pins, and internal logic) to drive onto the global clock network. Table 2–2
lists how many PLLs, CLK[] pins, DPCLK[] pins, and global clock
networks are available in each Cyclone II device. CLK[] pins are
dedicated clock pins and DPCLK[] pins are dual-purpose clock pins.
Table 2–2. Cyclone II Device Clock Resources
Number of
Global Clock
Networks
Number of
PLLs
Number of
CLK Pins
Number of
DPCLK Pins
Device
EP2C5
2
2
4
4
4
4
4
8
8
8
EP2C8
8
8
8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
16
16
16
16
16
20
20
20
20
20
16
16
16
16
16
Figures 2–11 and 2–12 show the location of the Cyclone II PLLs, CLK[]
inputs, DPCLK[] pins, and clock control blocks.
Altera Corporation
February 2007
2–17
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
