Cyclone II Architecture
Figure 2–12. EP2C15 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations
DPCLK[11..10]
CLK[11..8]
DPCLK[9..8]
CDPCLK7
CDPCLK6
2
2
4
4
PLL 3
PLL 2
3
CDPCLK5
DPCLK7
CDPCLK0
(2)
(2)
4
Clock Control
Block (1)
GCLK[15..0]
3
DPCLK0
CLK[3..0]
DPCLK1
16
16
16
CLK[7..4]
4
4
16
DPCLK6
Clock Control
Block (1)
GCLK[15..0]
4
3
(2)
(2)
CDPCLK4
CDPCLK1
3
4
PLL 1
PLL 4
4
2
2
CDPCLK2
CLK[15..12]
CDPCLK3
DPCLK[3..2]
DPCLK[5..4]
Notes to Figure 2–12:
(1) There are four clock control blocks on each side.
(2) Only one of the corner CDPCLKpins in each corner can feed the clock control block at a time. The other CDPCLKpins
can be used as general-purpose I/O pins.
Altera Corporation
February 2007
2–19
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
