I/O Structure & Features
Figure 2–27. DDR SDRAM Interfacing
DQS
DQ
LE
Register
LE
Register
OE
OE
t
Adjacent LAB LEs
LE
LE
Register
Register
LE
Register
LE
Register
V
DataA
DataB
LE
Register
LE
Register
CC
LE
Register
LE
Register
LE
Register
LE
Register
LE
Register
GND
clk
Clock Delay
Control Circuitry
PLL
Global Clock
en/dis
-90˚ Shifted clk
Resynchronizing
to System Clock
Clock Control
Block
Dynamic Enable/Disable
Circuitry
ENOUT
ena_register_mode
f
For more information on Cyclone II external memory interfaces, see the
External Memory Interfaces chapter in Volume 1 of the Cyclone II Device
Handbook.
2–48
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
