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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Power-On Reset Circuitry  
For Cyclone II devices, wake-up time consists of power-up, POR,  
configuration, and initialization. The device must properly go through all  
four stages to configure correctly and begin operation. You can calculate  
wake-up time using the following equation:  
Wake-Up Time = V Ramp Time + POR Time + Configuration Time + Initialization Time  
CC  
Figure 4–3 illustrates the components of wake up time.  
Figure 4–3. Cyclone II Wake-Up Time  
Voltage  
V
Minimum  
CC  
Time  
V
Ramp  
CC  
Time  
POR Time  
Configuration Time  
Initialization  
Time  
User  
Mode  
Note to Figure 4–3:  
(1) VCC ramp must be monotonic.  
The VCC ramp time and POR time will depend on the device  
characteristics and the power supply used in your system. The fast-on  
devices require a maximum VCC ramp time of 2 ms and have a maximum  
POR time of 12 ms.  
Configuration time will depend on the configuration mode chosen and  
the configuration file size. You can calculate configuration time by  
multiplying the number of bits in the configuration file with the period of  
the configuration clock. For fast configuration times, you should use  
Passive Serial (PS) configuration mode with maximum DCLK frequency  
of 100 MHz. In addition, you can use compression to reduce the  
configuration file size and speed up the configuration time. The tCD2UM  
or tCD2UMC parameters will determine the initialization time.  
1
For more information on the tCD2UM or tCD2UMC parameters, refer  
to the Configuring Cyclone II Devices chapter in the Cyclone II  
Device Handbook.  
4–6  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
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