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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Hot-Socketing Feature Implementation in Cyclone II Devices  
Figure 4–1. Hot-Socketing Circuit Block Diagram for Cyclone II Devices  
Power-On  
Reset  
Monitor  
Output  
Weak  
Pull-Up  
R
Output Enable  
Resistor  
Voltage  
Tolerance  
Control  
Hot Socket  
PAD  
Output  
Pre-Driver  
Input Buffer  
to Logic Array  
The POR circuit monitors VCCINT voltage level and keeps I/O pins  
tri-stated until the device is in user mode. The weak pull-up resistor (R)  
from the I/O pin to VCCIO keeps the I/O pins from floating. The voltage  
tolerance control circuit permits the I/O pins to be driven by 3.3 V before  
VCCIO and/or VCCINT are powered, and it prevents the I/O pins from  
driving out when the device is not in user mode.  
f
For more information, see the DC Characteristics & Timing Specifications  
chapter in Volume 1 of the Cyclone II Device Handbook for the value of the  
internal weak pull-up resistors.  
Figure 4–2 shows a transistor level cross section of the Cyclone II device  
I/O buffers. This design ensures that the output buffers do not drive  
when VCCIO is powered before VCCINT or if the I/O pad voltage is higher  
than VCCIO. This also applies for sudden voltage spikes during hot  
socketing. The VPAD leakage current charges the voltage tolerance control  
circuit capacitance.  
4–4  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
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