Selectable I/O Standards in Cyclone II Devices
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Cyclone II FPGA (EP2C15 or larger)
Altera PCI Express Compiler ×1 MegaCore® function
External PCI Express transceiver/PHY
2.5-V LVTTL (EIA/JEDEC Standard EIA/JESD8-5)
The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This
standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 2.5-V devices.
The 2.5-V standard does not require input reference voltages or board
terminations. Cyclone II devices support input and output levels for
2.5-V LVTTL.
2.5-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-5)
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 2.5-V parts.
The 2.5-V standard does not require input reference voltages or board
terminations. Cyclone II devices support input and output levels for
2.5-V LVCMOS.
SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A)
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed double data rate (DDR) SDRAM
interfaces. This standard defines the input and output specifications for
devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V.
This standard improves operations in conditions where a bus must be
isolated from large stubs. The SSTL-2 standard specifies an input voltage
range of – 0.3 V ≤VI ≤VCCIO + 0.3 V. SSTL-2 requires a VREF value of 1.25 V
and a VTT value of 1.25 V connected to the termination resistors (refer to
Figures 10–1 and 10–2).
Altera Corporation
February 2008
10–7
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
