Supported I/O Standards
1.8-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-7)
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 1.8-V parts.
The 1.8-V standard does not require input reference voltages or board
terminations. Cyclone II devices support input and output levels for
1.8-V LVCMOS.
SSTL-18 Class I and II
The 1.8-V SSTL-18 standard is formulated under JEDEC Standard,
JESD815: Stub Series Terminated Logic for 1.8V (SSTL-18).
The SSTL-18 I/O standard is a 1.8-V memory bus standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT, with the
termination resistors connected to both. There are no class definitions for
the SSTL-18 standard in the JEDEC specification. The specification of this
I/O standard is based on an environment that consists of both series and
parallel terminating resistors. Altera provides solutions to two derived
applications in JEDEC specification and names them class I and class II to
be consistent with other SSTL standards. Figures 10–5 and 10–6 show
SSTL-18 class I and II termination, respectively. Cyclone II devices
support both input and output levels.
Figure 10–5. 1.8-V SSTL Class I Termination
V
= 0.9 V
TT
Output Buffer
25 Ω
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.9 V
REF
10–10
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
