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EP2C35F484I8N 参数 Datasheet PDF下载

EP2C35F484I8N图片预览
型号: EP2C35F484I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Selectable I/O Standards in Cyclone II Devices  
Table 10–1. Cyclone II Supported I/O Standards and Constraints (Part 2 of 2)  
Top and  
Bottom I/O  
Pins  
VCCIO Level  
Side I/O Pins  
I/O Standard  
Type  
CLK, UserI/O CLK,  
User I/O  
Pins  
Input Output  
PLL_OUT  
DQS  
Pins  
DQS  
Differential HSTL-15 class I Pseudo  
(4)  
1.5 V  
v (6)  
or class II  
differential (3)  
1.5 V  
(4)  
v
v
(5)  
(5)  
Differential HSTL-18 class I Pseudo  
(4)  
1.8 V  
v (6)  
or class II  
differential (3)  
1.8 V  
(4)  
v
v
(5)  
(5)  
LVDS  
Differential  
Differential  
Differential  
2.5 V 2.5 V  
v
v
v
v
v
RSDS and mini-LVDS (7)  
LVPECL (8)  
(4)  
2.5 V  
v
v
v
3.3 V/  
2.5 V/  
1.8 V/  
1.5 V  
(4)  
v
v
Notes to Table 10–1:  
(1) These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.  
(2) PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and  
bottom I/O pins.  
(3) Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed  
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and  
SSTL inputs and only decode one of them.  
(4) This I/O standard is not supported on these I/O pins.  
(5) This I/O standard is only supported on the dedicated clock pins.  
(6) PLL_OUTdoes not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.  
(7) mini-LVDS and RSDS are only supported on output pins.  
(8) LVPECL is only supported on clock inputs, not DQS and dual-purpose clock pins.  
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)  
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended  
standard used for 3.3-V applications. The LVTTL standard defines the DC  
interface parameters for digital circuits operating from a 3.0-/3.3-V  
power supply and driving or being driven by LVTTL-compatible devices.  
The LVTTL input standard specifies a wider input voltage range of  
– 0.3 V VI 3.9 V. Altera recommends an input voltage range of  
– 0.5 V VI 4.1 V.  
Altera Corporation  
February 2008  
10–3  
Cyclone II Device Handbook, Volume 1  
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