Operational Modes
Figure 12–4. 9-Bit Multiplier Mode
signa (1)
signb (1)
aclr
clock
ena
D
Q
Data A 0 [8..0]
Data B 0 [8..0]
ENA
Data Out 0 [17..0]
D
Q
CLRN
ENA
CLRN
D
Q
ENA
CLRN
9 × 9 Multiplier
D
Q
Q
Data A 1 [8..0]
Data B 1 [8..0]
ENA
Data Out 1 [17..0]
D
Q
CLRN
ENA
CLRN
D
ENA
CLRN
9 × 9 Multiplier
Embedded Multiplier
Note to Figure 12–4:
(1) If necessary, you can send these signals through one register to match the data signal path.
All 9-bit multiplier inputs and results can be independently sent through
registers. The multiplier inputs can accept signed integers, unsigned
integers, or a combination of both. Each embedded multiplier only has
one signasignal to control the sign representation of both data A inputs
(one for each 9 × 9 multiplier) and one signbsignal to control the sign
representation of both data B inputs. Therefore, all of the data A inputs
feeding the same embedded multiplier must have the same sign
representation. Similarly, all of the data B inputs feeding the same
embedded multiplier must have the same sign representation.
12–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
