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EP2C20F256C8N 参数 Datasheet PDF下载

EP2C20F256C8N图片预览
型号: EP2C20F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 可编程逻辑PC时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Embedded Multipliers in Cyclone II Devices  
18-Bit Multipliers  
Each embedded multiplier can be configured to support a single  
18 × 18 multiplier for input widths from 10- to 18-bits. Figure 12–3 shows  
the embedded multiplier configured to support an 18-bit multiplier.  
Figure 12–3. 18-Bit Multiplier Mode  
signa (1)  
signb (1)  
aclr  
clock  
ena  
D
Q
Data A [17..0]  
Data B [17..0]  
ENA  
Data Out [35..0]  
D
Q
CLRN  
ENA  
CLRN  
D
Q
ENA  
CLRN  
18 × 18 Multiplier  
Embedded Multiplier  
Note to Figure 12–3:  
(1) If necessary, you can send these signals through one register to match the data signal path.  
All 18-bit multiplier inputs and results can be independently sent through  
registers. The multiplier inputs can accept signed integers, unsigned  
integers or a combination of both. Additionally, you can change the  
signaand signbsignals dynamically and can send these signals  
through dedicated input registers.  
9-Bit Multipliers  
Each embedded multiplier can also be configured to support two  
9 × 9 independent multipliers for input widths up to 9-bits. Figure 12–4  
shows the embedded multiplier configured to support two 9-bit  
multipliers.  
Altera Corporation  
February 2007  
12–7  
Cyclone II Device Handbook, Volume 1  
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