Embedded Multipliers in Cyclone II Devices
data A signal through a register and send the data B signal directly to the
multiplier). The following control signals are available to each register
within the embedded multiplier:
■
■
■
clock
clock enable
asynchronous clear
All input and output registers within a single embedded multiplier are
fed by the same clock, clock enable, or asynchronous clear signal.
Multiplier Stage
The multiplier stage supports 9 × 9 or 18 × 18 multipliers as well as other
smaller multipliers in between these configurations. See “Operational
Modes” on page 12–6 for details. Depending on the data width or
operational mode of the multiplier, a single embedded multiplier can
perform one or two multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signaand signb, control whether a multiplier’s input is a
signed or unsigned value. If the signasignal is high, the data A operand
is a signed number, and if the signasignal is low, the data A operand is
an unsigned number. Table 12–3 shows the sign of the multiplication
result for the various operand sign representations. The result of the
multiplication is signed if any one of the operands is a signed value.
Table 12–3. Multiplier Sign Representation
Data A
Data B
Result
signa Value
Logic Level
signb Value
Logic Level
Unsigned
Unsigned
Signed
Low
Low
High
High
Unsigned
Signed
Low
High
Low
High
Unsigned
Signed
Signed
Signed
Unsigned
Signed
Signed
There is only one signaand one signbsignal for each embedded
multiplier. The signaand signbsignals can be changed dynamically to
modify the sign representation of the input operands at run time. You can
send the signaand signbsignals through a dedicated input register.
The multiplier offers full precision regardless of the sign representation.
Altera Corporation
February 2007
12–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
