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EP2C20F256C8N 参数 Datasheet PDF下载

EP2C20F256C8N图片预览
型号: EP2C20F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 可编程逻辑PC时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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11. High-Speed Differential  
Interfaces in Cyclone II  
Devices  
CII51011-2.2  
From high-speed backplane applications to high-end switch boxes,  
low-voltage differential signaling (LVDS) is the technology of choice.  
LVDS is a low-voltage differential signaling standard, allowing higher  
noise immunity than single-ended I/O technologies. Its low-voltage  
swing allows for high-speed data transfers, low power consumption, and  
reduced electromagnetic interference (EMI). LVDS I/O signaling is a data  
interface standard defined in the TIA/EIA-644 and IEEE Std. 1596.3  
specifications.  
Introduction  
The reduced swing differential signaling (RSDS) and mini-LVDS  
standards are derivatives of the LVDS standard. The RSDS and  
mini-LVDS I/O standards are similar in electrical characteristics to  
LVDS, but have a smaller voltage swing and therefore provide increased  
power benefits and reduced EMI. National Semiconductor Corporation  
and Texas Instruments introduced the RSDS and mini-LVDS  
specifications, respectively. Currently, many designers use these  
specifications for flat panel display links between the controller and the  
drivers that drive display column drivers. Cyclone® II devices support  
the RSDS and mini-LVDS I/O standards at speeds up to 311 megabits per  
second (Mbps) at the transmitter.  
Altera® Cyclone II devices can transmit and receive data through LVDS  
signals at a data rate of up to 640 Mbps and 805 Mbps, respectively. For  
the LVDS transmitter and receiver, the Cyclone II device’s input and  
output pins support serialization and deserialization through internal  
logic.  
This chapter describes how to use Cyclone II I/O pins for differential  
signaling and contains the following topics:  
Cyclone II high-speed I/O banks  
Cyclone II high-speed I/O interface  
LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and  
differential SSTL I/O standards support in Cyclone II devices  
High-speed I/O timing in Cyclone II devices  
Design guidelines  
Cyclone II device I/O banks are shown in Figures 11–1 and 11–2. The  
EP2C5 and EP2C8 devices offer four I/O banks and EP2C15, EP2C20,  
EP2C35, EP2C50, and EP2C70 devices offer eight I/O banks. A subset of  
Cyclone II High-  
Speed I/O Banks  
Altera Corporation  
February 2007  
11–1  
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