Cyclone II Memory Blocks
Figure 8–20. Cyclone II Single-Clock Mode in Single-Port Mode
Notes (1), (2)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
Data In
512 ´ 8
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Address
D
ENA
To MultiTrack
Interconnect (2)
Data Out
Byte Enable
D
Q
ENA
D
ENA
Address
Clock Enable
addressstall
wren
Write Enable
Write
Pulse
Generator
D
ENA
Q
enable
clock
Notes to Figure 8–20:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) See the Cyclone II Device Family Data Sheet in Volume 1 of the Cyclone II Device Handbook for more information on the
MultiTrack interconnect.
Power-Up Conditions & Memory Initialization
The Cyclone II memory block outputs always power-up to zero,
regardless of whether the output registers are used or bypassed. Even if
an MIF pre-loads the contents of the memory block, the outputs still
power up cleared. For example, if address 0 is pre-initialized to FF, M4K
blocks power up with the output at 00. A subsequent read after power up
from address 0 outputs the pre-initialized value of FF.
Altera Corporation
February 2008
8–27
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
