Clock Modes
Figure 8–19. Cyclone II Single-Clock Mode in Simple Dual-Port Mode
Notes (1), (2)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
Data In
512 ´ 8
data[ ]
D
ENA
Q
Q
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
Read Address
D
ENA
To MultiTrack
Interconnect (2)
Data Out
Byte Enable
D
Q
ENA
byteena[ ]
D
ENA
Q
Q
wraddress[ ]
Write Address
D
ENA
Read Address
Clock Enable
rd_addressstall
wr_addressstall
Write Address
Clock Enable
(1)
rden
Read Enable
Write Enable
D
Q
ENA
wren
Write
Pulse
Generator
D
ENA
Q
enable
clock
Notes to Figure 8–19:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) See the Cyclone II Device Family Data Sheet in volume 1 of the Cyclone II Device Handbook for more information on the
MultiTrack interconnect.
8–26
Altera Corporation
February 2008
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
