Overview
Table 8–1. Summary of M4K Memory Features (Part 2 of 2)
Feature
M4K Blocks
Packed mode
v
v
v
v
v
v
v
v
v
v
v
v
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode (2)
ROM mode
FIFO buffer (2)
Simple dual-port mixed width support
True dual-port mixed width support
Memory Initialization File (.mif)
Mixed-clock mode
Power-up condition
Register clears
Outputs cleared
Output registers only
Same-port read-during-write
New data available at positive clock
edge
Mixed-port read-during-write
Old data available at positive clock
edge
Notes to Table 8–1:
(1) Maximum performance information is preliminary until device characterization.
(2) FIFO buffers and embedded shift registers require external logic elements (LEs)
for implementing control logic.
Table 8–2 shows the capacity and distribution of the M4K memory blocks
in each Cyclone II device family member.
Table 8–2. Number of M4K Blocks in Cyclone II Devices (Part 1 of 2)
Device
M4K Blocks
Total RAM Bits
EP2C5
EP2C8
26
36
119,808
165,888
239,616
239,616
483,840
EP2C15
EP2C20
EP2C35
52
52
105
8–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
