Clocking
Table 7–8 shows the clock sources connectivity to the global clock
networks.
Table 7–8. Global Clock Network Connections (Part 1 of 3)
Global Clock Networks
All Cyclone II Devices EP2C15 through EP2C70 Devices Only
Global Clock
Network Clock
Sources
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK0/LVDSCLK0p
CLK1/LVDSCLK0n
CLK2/LVDSCLK1p
CLK3/LVDSCLK1n
CLK4/LVDSCLK2p
CLK5/LVDSCLK2n
CLK6/LVDSCLK3p
CLK7/LVDSCLK3n
CLK8/LVDSCLK4n
CLK9/LVDSCLK4p
CLK10/LVDSCLK5n
CLK11/LVDSCLK5p
CLK12/LVDSCLK6n
CLK13/LVDSCLK6p
CLK14/LVDSCLK7n
CLK15/LVDSCLK7p
PLL1_c0
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL1_c1
v
v
PLL1_c2
PLL2_c0
v
v
v
v
v
v
PLL2_c1
v
v
PLL2_c2
PLL3_c0
v
v
v
v
v
v
PLL3_c1
v
v
PLL3_c2
7–22
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
