PLLs in Cyclone II Devices
locked
When the lockedport output is a logic high level, this indicates a stable
PLL clock output in phase with the PLL reference input clock. The
lockedport may toggle as the PLL begins tracking the reference clock.
The lockedport of the PLL can feed any general-purpose I/O pin or LEs.
The lockedsignal is optional, but is useful in monitoring the PLL lock
process.
The lockedoutput indicates that the PLL has locked onto the reference
clock. You may need to gate the locked signal for use as a system-control
signal. Either a gated lockedsignal or an ungated lockedsignal from
the lockedport can drive the logic array or an output pin. Cyclone II
PLLs include a programmable counter that holds the lockedsignal low
for a user-selected number of input clock transitions. This allows the PLL
to lock before transitioning the lockedsignal high. You can use the
Quartus II software to set the 20-bit counter value. The device resets and
enables both the counter and the PLL simultaneously upon power-up
and/or the assertion of the pllenablesignal. To ensure correct lock
circuit operation, and to ensure that the output clocks have the correct
phase relationship with respect to the input clock, Altera recommends
that the input clock be running before the Cyclone II device is configured.
Figure 7–9 shows the timing waveform for LOCKED and gated LOCKED
signals.
Figure 7–9. Timing Waveform for LOCKED & Gated LOCKED Signals
PLLENA
Reference Clock
Feedback Clock
Locked
Filter Counter
Reaches
Value Count
Gated Lock
Altera Corporation
February 2007
7–19
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
