PLLs in Cyclone II Devices
See the DC & Switching Characteristics chapter in Volume 1 of the
Cyclone II Device Handbook for information on PLL timing specifications.
PLL
Specifications
Cyclone II devices provide up to 16 dedicated clock pins (CLK[15..0])
that can drive the global clock networks. The smaller Cyclone II devices
(EP2C5 and EP2C8 devices) support four dedicated clock pins on each
side (left and right) capable of driving a total of eight global clock
networks, while the larger devices (EP2C15 devices and larger) support
four clock pins on all four sides of the device. These clock pins can drive
a total of 16 global clock networks.
Clocking
Table 7–7 shows the number of global clocks available across the
Cyclone II family members.
Table 7–7. Number of Global Clocks Available in Cyclone II Devices
Device
Number of Global Clocks
EP2C5
8
EP2C8
8
EP2C15
EP2C20
EP2C35
EP2C50
EP2C70
16
16
16
16
16
Global Clock Network
Global clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device (IOEs, logic array blocks
(LABs), dedicated multiplier blocks, and M4K memory blocks) can use
the global clock networks as clock sources. These clock network resources
can also be used for control signals, such as clock enables and
synchronous or asynchronous clears fed by an external pin. Internal logic
can also drive the global clock networks for internally generated global
clocks and asynchronous clears, clock enables, or other control signals
with high fan-out.
Altera Corporation
February 2007
7–21
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
