DC Characteristics and Timing Specifications
February 2007
v3.1
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Added document revision history.
Added VCCA minimum and maximum limitations in
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Table 5–1.
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Updated Note (1) in Table 5–2.
Updated the maximum VCC rise time for Cyclone II
“A” devices in Table 5–2.
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Updated RCONF information in Table 5–3.
Changed VI to Ii in Table 5–3.
Updated LVPECL clock inputs in Note (6) to
Table 5–8.
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Updated Note (1) to Table 5–12.
Updated CVREF capacitance description in
Table 5–13.
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Updated “Timing Specifications” section.
Updated Table 5–45.
Added Table 5–46 with information on toggle rate
derating factors.
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Corrected calculation of the period based on a
640 Mbps data rate as 1562.5 ps in Note (2) to
Table 5–50.
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Updated “PLL Timing Specifications” section.
Updated VCO range of 300–500 MHz in Note (3) to
Table 5–54.
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Updated chapter with extended temperature
information.
December 2005 Updated PLL Timing Specifications
v2.2
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November 2005 Updated technical content throughout.
v2.1
July 2005
v2.0
Updated technical content throughout.
November 2004 Updated the “Differential I/O Standards” section.
v1.1
Updated Table 5–54.
June 2004
v1.0
Added document to the Cyclone II Device Handbook.
Altera Corporation
February 2008
5–75
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
