DC Characteristics and Timing Specifications
The actual half period is then = 3000 ps – 155 ps = 2845 ps
Table 5–58. Maximum DCD for DDIO Output on Column I/O Pins with PLL in
the Clock Path Notes (1), (2)
Column I/O Pins in the Clock Path
C6
C7
C8
Unit
LVCMOS
285
305
175
190
605
125
195
130
135
135
165
220
190
125
195
130
132
135
165
220
190
110
125
110
400
405
195
205
645
210
195
240
270
240
240
335
210
210
195
240
270
240
240
335
210
120
125
120
445
460
285
260
645
245
195
245
330
240
285
335
375
245
195
245
330
240
285
335
375
125
275
125
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
LVTTL
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential HSTL-18 Class I
Differential HSTL-18 Class II
Differential HSTL-15 Class I
Differential HSTL-15 Class II
LVDS
Simple RSDS
Mini-LVDS
Notes to Table 5–58:
(1) The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
(2) Numbers are applicable for commercial, industrial, and automotive devices.
Altera Corporation
February 2008
5–73
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
