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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
Figure 4–10. C4 Interconnect Connections  
Note (1)  
C4 Interconnect  
Drives Local and R4  
Interconnects  
up to Four Rows  
C4 Interconnect  
Driving Up  
LAB  
Row  
Interconnect  
Adjacent LAB can  
drive onto neighboring  
LAB's C4 interconnect  
Local  
Interconnect  
C4 Interconnect  
Driving Down  
Note to Figure 4–10:  
(1) Each C4 interconnect can drive either up or down four rows.  
C8 interconnects span eight LABs, M512, or M4K blocks up or down from  
a source LAB. Every LAB has its own set of C8 interconnects to drive  
either up or down. C8 interconnect connections between the LABs in a  
column are similar to the C4 connections shown in Figure 4–10 with the  
exception that they connect to eight LABs above and below. The C8  
Altera Corporation  
February 2005  
4–15  
Stratix GX Device Handbook, Volume 1  
 
 
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