Source-Synchronous Signaling With DPA
To manage the alignment procedure, a state machine should be built in
the FPGA logic array to generate the realignment signal. The following
guidelines outline the requirements for this state machine.
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The design must include an input synchronizing register to ensure
that data is synchronized to the ×W/J clock.
After the state machine, use another synchronizing register to
capture the generated rx_channel_data_alignsignal and
synchronize it to the ×W/J clock.
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Because the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two W/J clock periods.
To guarantee the state machine does not incorrectly generate
multiple rx_channel_data_alignpulses to shift a single bit, the
state machine must hold the rx_channel_data_alignsignal low
for at least three ×1 clock periods between pulses.
Altera Corporation
August 2005
3–15
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
