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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Source-Synchronous Signaling With DPA  
Figure 3–10. Misaligned Captured Bits  
Correct Alignment  
0
1
2
3
6
4
7
5
0
6
1
7
2
Incorrect Alignment  
3
4
5
The dynamic phase selector and synchronizer align the clock and data  
based on the power-up of both communicating devices, and the channel  
to channel skew. However, the dynamic phase selector and synchronizer  
cannot determine the byte boundary, and the data may need to be  
byte-aligned. The dynamic phase aligner’s data realignment circuitry  
shifts data bits to correct bit misalignments.  
The Stratix GX circuitry contains a data-realignment feature controlled by  
the logic array. Stratix GX devices perform data realignment on the  
parallel data after the deserialization block. The data realignment can be  
performed per channel for more flexibility. The data alignment operation  
requires a state machine to recognize a specific pattern. The procedure  
requires the bits to be slipped on the data stream to correctly align the  
incoming data to the start of the byte boundary.  
The DPA uses its realignment circuitry and the global clock for data  
realignment. Either a device pin or the logic array asserts the internal  
rx_channel_data_alignnode to activate the DPA data-realignment  
circuitry. Switching this node from low to high activates the realignment  
circuitry and the data being transferred to the logic array is shifted by  
one bit. The data realignment block cannot be bypassed. However, if the  
rx_channel_data_alignis not turned on (through the altvlds  
MegaWizard Plug-In Manager), or when it is not toggled, it only acts as a  
register latency.  
A state machine and additional logic can monitor the incoming parallel  
data and compare it against a known pattern. If the incoming data pattern  
does not match the known pattern, you can activate the  
rx_channel_data_alignnode again. Repeat this process until the  
realigner detects the desired match between the known data pattern and  
incoming parallel data pattern.  
Altera Corporation  
August 2005  
3–13  
Stratix GX Device Handbook, Volume 1  
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