Introduction
TM
Unlike the de-skew function in APEX 20KE and APEX 20KC devices,
you do not have to use a fixed training pattern with DPA in Stratix GX
devices. Table 3–1 shows the differences between source-synchronous
circuitry with DPA and source-synchronous circuitry without DPA
circuitry in Stratix GX devices.
Table 3–1. Source-Synchronous Circuitry With & Without DPA
Source-Synchronous Circuitry
Feature
Without DPA
With DPA
Data rate
300 to 840 Megabits per 300 Mbps to 1 Gbps
second (Mbps)
Deserialization factors
Clock frequency
Interface pins
1, 2, 4, 8, 10
8, 10
10 to 717 MHz
I/O banks 1 and 2
Dedicated inputs
74 to 717 MHz
I/O banks 1 and 2
Dedicated inputs
Receiver pins
DPA Input Support
Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to
support differential I/O standards at speeds up to 1 Gbps with DPA (or
up to 840 Mbps without DPA). Stratix GX device source-synchronous
circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each
with a supply voltage of 3.3 V. Refer to the High-Speed Source-Synchronous
Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX
Device Handbook, Volume 2 for more information on these I/O standards.
Transmitter pins can be either input or output pins for single-ended I/O
standards. Refer to Table 3–2.
Table 3–2. Bank 1 & 2 Input Pins
Input Pin Type
I/O Standard
Receiver Pin
Transmitter Pin
Differential
Differential
Single ended
Input only
Input only
Output only
Single ended
Input or output
Interface & Fast PLL
This section describes the number of channels that support DPA and their
relationship with the PLL in Stratix GX devices. EP1SGX10 and
EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices
3–6
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
