Source-Synchronous Signaling With DPA
Figure 3–1. Stratix GX High-Speed Interface Deserialized in ×10 Mode
Receiver Circuit
Serial Shift
Parallel
Parallel
Registers
Registers
Registers
RXIN+
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
RXIN−
Stratix GX
Logic Array
×W
×W/J (1)
RXCLKIN+
Fast
PLL (2)
RXLOADEN
TXLOADEN
RXCLKIN−
Notes to Figure 3–1:
(1) W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA).
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
(2) This figure does not show additional circuitry for clock or data manipulation.
Figure 3–2. Receiver Timing Diagram
Internal ×1 clock
Internal ×10 clock
RXLOADEN
Receiver
n – 1 n – 0
9
8
7
6
5
4
3
2
1
0
data input
Stratix GX Differential I/O Transmitter Operation
You can configure any of the Stratix GX differential output channels as a
transmitter channel. The differential transmitter serializes outbound
parallel data.
Altera Corporation
August 2005
3–3
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
