XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/(/K28.0/), denoted by //R//.
An //R//is added or deleted automatically based on the number of
words in the FIFO buffer.
8B/10B Decoder
The 8B/10B decoder converts the 10-bit encoded code group into 8-bit
data and 1 control bit. The 8B/10B decoder can be bypassed. The
following is a diagram of the conversion from a 10-bit encoded code
group into 8-bit data + 1-bit control.
Figure 2–20. 8B/10B Decoder Conversion
j
h
8
g
7
f
i
e
4
d
3
c
b
1
a
0
9
6
5
2
MSB received last
LSB received first
8b-10b conversion
+
Parallel data
7
6
5
F
4
3
2
1
0
ctrl
H
G
E
D
C
B
A
There are two optional error status ports available in the 8B/10B decoder,
rx_errdetectand rx_disperr. Table 2–7 shows the values of the
ports from a given error. These status signals are aligned with the code
group in which the error occurred.
Table 2–7. Error Signal Values
Types of Errors
rx_errdetect
rx_disperr
No errors
1’b0
1’b1
1’b1
1’b0
1’b0
1’b1
Invalid code groups
Disparity errors
2–24
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
ALTERA [ ALTERA CORPORATION ]
