EP1SGX40GF1020I6N 参数 Datasheet PDF下载

型号：	EP1SGX40GF1020I6N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用：	栅可编程逻辑
文件页数/大小：	279 页 / 3682 K
品牌：	ALTERA [ ALTERA CORPORATION ]

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Figure 2–27. EP1SGX40G Device Inter-Transceiver & Global Clock Connections

Note (1)

IQ0

IQ1

IQ2

Quad 0

IQ0

IQ1

Transmitter

PLL

Global Clocks,

I/O Bus,

General Routing

IQ2

Receiver

PLLs (1)

Global Clocks,

I/O Bus,

General Routing

Quad 1

Quad 4

Quad 2

IQ0

IQ1

Transmitter

PLL

Global Clocks,

I/O Bus,

General Routing

IQ2

Receiver

PLLs (1)

Global Clocks,

I/O Bus,

General Routing

PLD

Global

Clocks

IQ0

IQ1

Transmitter

PLL

Global Clocks,

I/O Bus,

General Routing

IQ2

Receiver

PLLs (1)

Global Clocks,

I/O Bus,

General Routing

IQ0

IQ1

Transmitter

PLL

Global Clocks,

I/O Bus,

General Routing

IQ2

Receiver

PLLs (1)

Global Clocks,

I/O Bus,

General Routing

Quad 3

IQ0

IQ1

Transmitter

PLL

Global Clocks,

I/O Bus,

General Routing

IQ2

Receiver

PLLs (1)

Global Clocks,

I/O Bus,

General Routing

Notes to Figure 2–27:

(1) IQ lines are inter-transceiver block lines.

(2) There are four receiver PLLs in each transceiver block.

The receiver PLL can also drive the fast regional, regional clocks, and

local routing adjacent to the associated transceiver block. Figures 2–28

through 2–31 show which fast regional and regional clock resource can be

used by the recovered clock.

2–32

Stratix GX Device Handbook, Volume 1

Altera Corporation

February 2005

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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

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