Stratix GX Transceivers
Figure 2–26. EP1SGX25F Device Inter-Transceiver & Global Clock Connections
Note (1)
IQ0
IQ1
IQ2
Quad 0
IQ0
IQ1
Transmitter
PLL
Global Clocks,
I/O Bus,
General Routing
refclkb
/2
4
IQ2
Receiver
PLLs (2)
Global Clocks,
I/O Bus,
General Routing
Quad 1
Quad 2
Quad 3
IQ0
IQ1
Transmitter
PLL
Global Clocks,
I/O Bus,
General Routing
/2
/2
/2
4
4
4
PLD
Global
Clocks
IQ2
Receiver
PLLs (2)
Global Clocks,
I/O Bus,
General Routing
16
IQ0
IQ1
Transmitter
PLL
Global Clocks,
I/O Bus,
General Routing
IQ2
Receiver
PLLs (2)
Global Clocks,
I/O Bus,
General Routing
IQ0
IQ1
Transmitter
PLL
Global Clocks,
I/O Bus,
General Routing
IQ2
Receiver
PLLs (2)
Global Clocks,
I/O Bus,
General Routing
Notes to Figure 2–26:
(1) IQ lines are inter-transceiver block lines.
(2) There are four receiver PLLs in each transceiver block.
Altera Corporation
February 2005
2–31
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
