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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 6–12. 1.5-V I/O Specifications  
Symbol  
Parameter  
Conditions  
Minimum  
Maximum  
Units  
VOL  
Low-level output voltage  
IOL = 2 mA (1)  
0.25 × VCCIO  
V
Note to Tables 6–8 through 6–12:  
(1) Drive strength is programmable according to values in found in the Stratix GX Architecture chapter of the  
Stratix GX Device Handbook, Volume 1.  
Figures 6–1 and 6–2 show receiver input and transmitter output  
waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V  
PCML, LVPECL, and HyperTransport technology).  
Figure 6–1. Receiver Input Waveforms for Differential I/O Standards  
Single-Ended Waveform  
Positive Channel (p) = V  
OH  
V
OD  
Negative Channel (n) = V  
OL  
V
CM  
Ground  
Differential Waveform  
(V  
OD  
(Differential) = 2 x V (single-ended))  
OD  
V
OD  
p n = 0 V  
V
OD  
6–12  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
August 2005  
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