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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 7 of 7)  
-6 Commercial &  
Industrial Speed  
-7 Commercial &  
Industrial Speed  
Grade  
-5 Commercial  
Speed Grade (1)  
Symbol /  
Description  
Grade  
Conditions  
Unit  
(1)  
(1)  
Min Typ  
Max  
Min Typ  
Max  
Min Typ  
Max  
Outputreturn 100 MHz to  
loss 2.5 GHz  
–10  
–10  
–10  
dB  
Notes to Table 6–7:  
(1) All numbers for the -6 and -7 speed grades are for both commercial and industrial unless specified otherwise in the  
Conditions column. Speed grade -5 is available only for commercial specifications.  
(2) Not all VID and equalizer values will get the same results. The condition for the specification was that the VID before  
jitter was added is 1,000 mV and the equalizer was set to the maximum condition of 111 (equalizer control setting  
= 4 in the MegaWizard Plug-In Manager).  
(3) Number of parallel clocks.  
(4) Receive latency delay from serial receiver indata to parallel receiver data.  
(5) Per IEEE Standard 802.3ae @ 3.125 for –5 and –6.  
(6) The specification is for channel aligner tolerance.  
(7) UI = Unit Interval.  
(8) Run-length conditions are true for all data rates, but the average transition density must be enough to keep the  
receiver phase aligned and the overall data must be DC balanced.  
(9) Not all combinations of VOD and pre-emphasis will get the same results.  
(10) The numbers are for 3.125-Gbps data rate for –5 and –6 devices and 2.5 Gbps for –7 devices.  
(11) Transmitter latency delay from parallel transceiver data to serial transceiver out data.  
Table 6–8. LVTTL Specifications  
Symbol  
Parameter  
Output supply voltage  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
Conditions  
Minimum  
3.0  
Maximum  
3.6  
Units  
VCCIO  
V
V
V
V
V
VIH  
VIL  
1.7  
4.1  
–0.5  
2.4  
0.7  
VOH  
VOL  
IOH = –4 to –24 mA (1)  
IOL = 4 to 24 mA (1)  
0.45  
Table 6–9. LVCMOS Specifications  
Symbol  
Parameter  
Conditions  
Minimum  
3.0  
Maximum  
3.6  
Units  
VCCIO  
Output supply voltage  
High-level input voltage  
Low-level input voltage  
V
V
V
VIH  
VIL  
1.7  
4.1  
–0.5  
0.7  
6–10  
Altera Corporation  
August 2005  
Stratix GX Device Handbook, Volume 1  
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