Timing Model
Table 4–87. EP1S60 External I/O Timing on Column Pins Using Global Clock Networks Note (1)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Max
tINSU
2.000
0.000
3.051
2.991
2.991
1.315
0.000
1.029
0.969
0.969
2.152
0.000
3.051
2.991
2.991
1.362
0.000
1.029
0.969
0.969
2.441
0.000
3.051
2.991
2.991
1.543
0.000
1.029
0.969
0.969
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.900
5.774
5.774
6.340
6.208
6.208
6.977
6.853
6.853
NA
NA
NA
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
2.196
2.070
2.070
2.303
2.171
2.171
2.323
2.199
2.199
NA
NA
NA
Table 4–88. EP1S60 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
NA
NA
NA
NA
NA
Max
tINSU
3.144
0.000
2.643
2.670
2.670
3.393
0.000
2.643
2.670
2.670
3.867
0.000
2.643
2.670
2.670
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.275
5.329
5.329
5.654
5.710
5.710
6.140
6.208
6.208
NA
NA
NA
tZX
4–52
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
