Timing Model
Tables 4–91 through 4–96 show the external timing parameters on column
and row pins for EP1S80 devices.
Table 4–91. EP1S80 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
NA
NA
NA
NA
NA
Max
tINSU
2.328
0.000
2.422
2.362
2.362
2.528
0.000
2.422
2.362
2.362
2.900
0.000
2.422
2.362
2.362
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
4.830
4.704
4.704
5.169
5.037
5.037
5.633
5.509
5.509
NA
NA
NA
tZX
Table 4–92. EP1S80 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Max
tINSU
1.760
0.000
2.761
2.701
2.701
0.462
0.000
1.661
1.601
1.601
1.912
0.000
2.761
2.701
2.701
0.606
0.000
1.661
1.601
1.601
2.194
0.000
2.761
2.701
2.701
0.785
0.000
1.661
1.601
1.601
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.398
5.272
5.272
5.785
5.653
5.653
6.339
6.215
6.215
NA
NA
NA
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
2.849
2.723
2.723
2.859
2.727
2.727
2.881
2.757
2.757
NA
NA
NA
4–54
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
