Timing Model
Tables 4–79 through 4–84 show the external timing parameters on column
and row pins for EP1S40 devices.
Table 4–79. EP1S40 External I/O Timing on Column Pins Using Fast Regional Clock Networks
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tINSU
2.696
0.000
2.506
2.446
2.446
2.907
0.000
2.506
2.446
2.446
3.290
0.000
2.506
2.446
2.446
2.899
0.000
2.698
2.638
2.638
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.015
4.889
4.889
5.348
5.216
5.216
5.809
5.685
5.685
7.286
7.171
7.171
tZX
Table 4–80. EP1S40 External I/O Timing on Column Pins Using Regional Clock Networks
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tINSU
2.413
0.000
2.668
2.608
2.608
1.385
0.000
1.117
1.057
1.057
2.581
0.000
2.668
2.608
2.608
1.376
0.000
1.117
1,057
1,057
2.914
0.000
2.668
2.608
2.608
1.609
0.000
1.117
1.057
1.057
2.938
0.000
2.869
2.809
2.809
1.837
0.000
1.117
1.057
1.057
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.254
5.128
5.128
5.628
5.496
5.496
6.132
6.008
6.008
7.307
7.192
7.192
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
2.382
2.256
2.256
2.552
2.420
2.420
2.504
2.380
2.380
2.542
2.427
2.427
4–48
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
