Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–37 through 4–42 describe the
Stratix device internal timing microparameters for LEs, IOEs, TriMatrix™
memory structures, DSP blocks, and MultiTrack interconnects.
Table 4–37. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
tSU
tH
tCO
tLUT
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Register minimum clock high or low time. The maximum core
clock frequency can be calculated by 1/(2 × tCLKHL).
Table 4–38. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU_R
tSU_C
tH
Row IOE input register setup time
Column IOE input register setup time
IOE input and output register hold time after clock
Row IOE input and output register clock-to-output delay
Column IOE input and output register clock-to-output delay
Row input pin to IOE combinatorial output
Column input pin to IOE combinatorial output
Row IOE data input to combinatorial output pin
Column IOE data input to combinatorial output pin
Minimum clear pulse width
tCO_R
tCO_C
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Register minimum clock high or low time. The maximum I/O
clock frequency can be calculated by 1/(2 × tCLKHL).
Performance may also be affected by I/O timing, use of PLL,
and I/O programmable settings.
4–22
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
