DC & Switching Characteristics
The DirectDrive™ technology and MultiTrack™ interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix device densities and speed grades. This section
describes and specifies the performance, internal, external, and PLL
timing specifications.
Timing Model
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 4–35 shows the status of the
Stratix device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Table 4–35. Stratix Device Timing Model Status
Device
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Preliminary
Final
v
v
v
v
v
v
v
Altera Corporation
July 2005
4–19
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
