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EP1S25F672I7N 参数 Datasheet PDF下载

EP1S25F672I7N图片预览
型号: EP1S25F672I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 25660-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用: LTE可编程逻辑
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
Pipeline/Post Multiply Register  
The output of 9 × 9- or 18 × 18-bit multipliers can optionally feed a register  
to pipeline multiply-accumulate and multiply-add/subtract functions.  
For 36 × 36-bit multipliers, this register will pipeline the multiplier  
function.  
Adder/Output Blocks  
The result of the multiplier sub-blocks are sent to the adder/output block  
which consist of an adder/subtractor/accumulator unit, summation unit,  
output select multiplexer, and output registers. The results are used to  
configure the adder/output block as a pure output, accumulator, a simple  
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit  
multiplier. You can configure the adder/output block to use output  
registers in any mode, and must use output registers for the accumulator.  
The system cannot use adder/output blocks independently of the  
multiplier. Figure 2–34 shows the adder and output stages.  
Altera Corporation  
July 2005  
2–61  
Stratix Device Handbook, Volume 1